A group of researchers based in Britain have managed to find new approaches to hardware addition and multiplication, two of the most basic functions of many modern-day chips. The new discoveries, it has been claimed, could result in chips running with performance reaching two times that of current chips.
The Oxford researchers, working for Automatic Parallel Designs, claim they can achieve this while utilising less die area and also say better power efficiency would result through using the new findings to re-design math circuitry (about 50% more energy efficiency than 0.13 micron technology according to the researchers). AutoPD also claim to be working with a major CPU manufacturer on a new floating point multiplier and the findings could influence chip makers in many areas including processor and DSP technology. The algorithms are also being considered by at least two other processor makers according to recent reports.
This research was the result of interest expressed when AutoPD visited a Design Automation Conference in 1999 where they were showcasing the Karakoram algorithm, which was a type of state machine encoding. They were demonstrating how Karakoram increased performance in that area, but when showcasing their work there were more people interested in a sub-section of their research which was the die-area reduction of hardware multipliers. This led them to return from the American conference and start work on this area in more detail, which has resulted in these new findings.