IBM and Advanced Micro Devices are stressing out their chips.
The companies, allies in developing semiconductor manufacturing
technology, will present two papers at a chip conference this week
outlining how they have reduced power consumption on chips made on the
65-nanometer process.
AMD and IBM have essentially added two technologies to their
manufacturing repertoire that strain the silicon layers inside their
chips. Straining makes the silicon layers more uniform and rigid, which
allows electrons to travel faster. This in turn lets engineers design
chips that perform better than existing models, or perform at a similar
level but consume less electricity.