Linus Torvalds, the father of Linux, is probably one of the most expressive tech bosses out there, and his takes are almost always very interesting whether you agree with them or not.
While discussing changes and additions to the new Linux KConfig (kernel configuration) build, Torvalds expressed his annoyance and disapproval of the AMD64 or x86_64 architecture feature levels. He wrote:
On second thought , let’s not go to x86-64 microarchitectural levels. ‘Tis a silly place"
The whole "v2", "v3", "v4" etc naming seems to be some crazy glibc artifact and is stupid and needs to die.
It has no relevance to anything. Please do *not* introduce that mind-fart into the kernel sources.
I have no idea who came up with the "microarchitecture levels" garbage, but as far as I can tell, it"s entirely unofficial, and it"s a completely broken model.
There is a very real model for microarchitectural features, and it"s the CPUID bits. Trying to linearize those bits is technically wrong, since these things simply aren"t some kind of linear progression.
And worse, it"s a "simplification" that literally adds complexity. Now instead of asking "does this CPU support the cmpxchgb16 instruction?", the question instead becomes one of "what the hell does "v3" mean again?"
So no. We are *NOT* introducing that idiocy in the kernel.
Linus
For those wondering, these x86-64 microarchitecture levels were introduced back in 2020 by Red Hat"s Florian Weimer. Initially, "Levels A, B, and C," were proposed, and later "Level D" was added too.
What these levels essentially do is classify CPU features in a temporal/chronological manner in an attempt to make it simpler to improve hardware and OS/software compatibility and synergy via better compilation optimizations:
- x86-64-v2 brings support (among other things) for vector instructions up to Streaming SIMD Extensions 4.2 (SSE4.2) and Supplemental Streaming SIMD Extensions 3 (SSSE3), the POPCNT instruction (useful for data analysis and bit-fiddling in some data structures), and CMPXCHG16B (a two-word compare-and-swap instruction useful for concurrent algorithms).
- x86-64-v3 adds vector instructions up to AVX2, MOVBE (for big-endian data access), and additional bit-manipulation instructions.
- x86-64-v4 includes vector instructions from some of the AVX-512 variants.
Linus Torvalds feels these architecture levels make things more convoluted rather than simplifying the matter as linearizing the progression of hardware instructions and features is not a realistic approach.
Here, Torvalds does make sense given that we often find that certain CPU instructions, like say AVX, may be present in some processor family but it goes away later on. A recent example is Intel introducing AVX-512 in 11th Gen Rocket Lake and then removing it later in succeeding generations.
It is noteworthy here that Linus Torvalds is now a luminary of the recently conceived x86 Ecosystem Advisory Group so his input can certainly hold some weight.