Thanks Toxikk & PROGAME for sending this in. Chip Giant Intel has confirmed the large caches (3MB and above) it will include on future versions of the Itanium and has also further explained its tie in with Ovonics on these chips, first revealed here some months ago.
Intel is delivering eleven papers at the Solid State conference. Along with this, Intel has now formally released details of the 3MB cache on chip which it claims will deliver 1.5 to two times performance over the current designs. The low latency level three cache which will be included in the McKinley design is expected to give better performance for the processor, which will be used in servers.
Intel, according to chief technical officer Pat Gelsinger, is facing the challenge of providing chips with high performance, low power, and low leakage.
To that end, the company will design circuits which will use a new design of arithmetic logic unit (ALU) to reduce circuitries, and is now capable of demonstrating a 5GHz chip at .13 micron process technology which can operate at room temperature. The test chip shows active power reduced by 23 per cent, and standby leakage reduced by 3.5 times.
News source: The Inquirer
Image: Detailed picture of the McKinley die - The Inquirer
Image: Intel block layout for the 5GHz processor - The Inquirer
