Intel Corporation is probably one of the most respected IT firms on the planet that manages to execute its roadmaps pretty flawlessly. Unfortunately, every rule has its exceptions and Intel may also run into problems that can become obstacles on the way of the world's largest chipmaker. From the original timeframe in Q2 2003 Intel postponed the release on highly-acclaimed Prescott processor to Q4 2003, but, as we know already, the actual massive availability of the 90nm chips is expected to be in the late Q1 2004 or even a bit later. Such delays in Prescott ramp also impacted the release of the future-generation Tejas processor, a Japanese source reported this week.
Both Tejas and Prescott processors are based on Intel's NetBurst architecture already utilized in Intel Pentium 4 processors. The Prescott and Tejas are expected to bring some advantages that include enhancements of the NetBurst paramount peculiarities that influence CPU performance the most. First of all, the L1 cache will be enlarged to 16 and 24KB in Prescott and Tejas processors respectively from Northwood's 8KB. Secondly, Tejas and Prescott will include 16K uOps Trace Cache, a substantial improvement over Northwood's 12K uOps. Thirdly, the L2 caches of Tejas and Prescott chips made using 90nm technology will be 1MB, while the 65nm Tejas is projected to have 2MB of L2. Additionally, in an attempt to lower the impact of deep-20+ stage pipeline on actual performance, Intel will implement a new, more efficient branch prediction mechanism in its forthcoming microprocessors. Finally, Intel will raise both core and PSB clocks, resulting in even faster computing speed of the next-generation NetBurst processors. Furthermore, following Intel's recent general policy, presuppose enhanced efficiency of the Hyper-Threading technology as well as several new instructions (Prescott New Instructions, Tejas New Instructions) to optimize certain operations with every new generation of NetBurst chips.
News source: X-bit labs
