WAY BACK IN THE DAYS when grass was greener, children were still beautiful, and computers ran at speeds today now reserved for PDAs, there was a little RAM technology we used called EDO that happened to use an interface system we called SIMM (Single Inline Memory Module). Along with having only half the transfer capability of modern DIMMs, (32-bit data paths vs. 64), SIMM technology required the end user to insert two modules simultaneously of identical density and configuration.
The invention of DIMM technology and its subsequent adoption around 1997 made the dual-module requirement obsolete, and up until now, module insertion limitations have been all-but nonexistent. Even RDRAM, which does have some restrictions on how it can be inserted, uses a C-RIMM terminator design to allow for the use of a smaller number of RIMMs.
With the rise of dual-channel DDR designs, however, we may be re-entering an era of more restrictive RAM configurations. This is less of an issue for the NVIDIA nForce2, because the Athlon's own bandwidth limitation make the additional bandwidth offered by a 128-bit solution generally spurious (though there are a few applications that benefit). In the case of the dual-channel DDR Pentium 4, however, the difference between single and dual channel DDR RAM performance is substantial.
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News source: The Inq
