At its Accelerated event, Intel had a bunch of stuff to announce regarding its node naming strategy and architecture roadmap for products that it will power through 2025 and beyond. It has also unveiled its first new transistor architecture in over a decade, and named it RibbonFET.
First up is Intel's new node naming strategy detailed in the roadmap seen above. The company is making these changes to offer customers a vivid view of process nodes as well as establish a consistent framework.
Intel 7 - previously known as Enhanced SuperFin - is targeted for Alder Lake in client machines and Sapphire Rapids for data centers. The latter will enter production phase in the first quarter of 2022. Next up is Intel 4 - previously known as 7nm -, the salient features of which can be seen in the graphic above. Intel 3 will be another incremental upgrade after that and will focus on "power and area improvements".
Finally, 2024 will see the advent of Intel 20A which will offer two breakthrough innovations in the way of RibbonFET and PowerVia. The former will be an implementation of a gate-all-around transistor and will allow for superior transistor switching speeds in a smaller footprint. The latter is an implementation of backside power delivery which optimizes the transmission of signals by eradicating the need for power routing on the wafer's front side. The company has tapped Qualcomm as a partner for this process.
From 2025 and beyond, Intel will be focusing on 18A, which will include enhancements to RibbonFET as well as next-gen High NA EUV. The firm will be partnering with ASML for these improvements. Intel's CEO Pat Gelsinger had the following to say regarding the company's ambitions:
Building on Intel’s unquestioned leadership in advanced packaging, we are accelerating our innovation roadmap to ensure we are on a clear path to process performance leadership by 2025. We are leveraging our unparalleled pipeline of innovation to deliver technology advances from the transistor up to the system level. Until the periodic table is exhausted, we will be relentless in our pursuit of Moore’s Law and our path to innovate with the magic of silicon.
Since the company is focused on Moore's Law, it also makes sense to talk about packaging enhancements planned for the next few years under its integrated device manufacturing (IDM) 2.0 model.
Embedded multi-die interconnect bridge (EMIB) has been used in products since 2017 and will continue to be used in Sapphire Rapids next year as well. After that, it will feature an incremental upgrade and will transition from a 55-micron bump pitch to 45 microns. Meanwhile, Foveros will be a 3D stacking solution and will be present in Meteor Lake for client products. It will have a bump pitch of 36 microns and a thermal design power range of 5-125W.
Next, we'll see Foveros Omni and Foveros Direct. The former will enable die segregation and is expected to hit mass production in 2023. On the other hand, Foveros Direct will be complementary to Omni, and will allow bump pitches of sub-10 microns, increased interconnect density, and copper-to-copper bonding for low-resistance interconnects. It will also be ready for volume manufacturing in 2023.
Intel plans to reveal more details about all these technologies at its InnovatiON event on October 27-28, 2021. It will be held in San Francisco and can be viewed online as well. You can find out more details here.
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